Two devices can share a signal wire if they take turns driving it. What happens in the moment between turns? Use two buffers in a Texas Instruments SN74HC125N to hand one test node from a high output to a low output. Record the node and both enable signals. One command leaves a short gap. The other creates a controlled overlap through two separate resistors, so you can see the electrical difference without directly tying opposing outputs together.
A buffer repeats a digital input at its output while it is enabled. This part also has a third output state called high impedance. In that state the output largely releases the wire. The output-enable input, abbreviated OE, is active low. A low level turns that channel on, and a high level releases it. Here OE_A and OE_B are names for the two control wires. With a buffer enabled, a high data input makes it source current and a low data input makes it sink current. Sourcing sends current out of the output and sinking draws current into it.
Use the exact SN74HC125N in its 14-pin plastic dual in-line package, abbreviated PDIP-14. Use the notch and TI's top-view diagram to find pin 1. Use a 5 V Arduino UNO R3 with the ATmega328P microcontroller, a breadboard, two 2.2 kΩ resistors, two 10 kΩ resistors and one 47 kΩ resistor, all 1% and rated at least 0.125 W. Use a 100 nF ceramic bypass capacitor rated at least 10 V. It supplies brief changes in current close to the chip. A scope with at least three channels and compensated 10× probes records the two controls and the shared node.
| U1 pin | Connection | Job |
|---|---|---|
| 1 /1OE | UNO D7, R3 10 kΩ to +5 V, scope channel 1 tip | OE_A, low enables the high branch. |
| 2 1A | +5 V | Fixed high input. |
| 3 1Y | R1 2.2 kΩ to BUS | Protected branch from output A. |
| 4 /2OE | UNO D8, R4 10 kΩ to +5 V, scope channel 2 tip | OE_B, low enables the low branch. |
| 5 2A | 0 V | Fixed low input. |
| 6 2Y | R2 2.2 kΩ to BUS | Protected branch from output B. |
| 7 GND | UNO GND, C1 return, probe ground clips | One common 0 V. |
| 10 /3OE, 13 /4OE | +5 V | Disable both unused buffers. |
| 9 3A, 12 4A | 0 V | Define both unused data inputs. |
| 8 3Y, 11 4Y | Leave open | Unused outputs. |
| 14 VCC | UNO 5V, C1 100 nF to pin 7 | Supply, with C1 close to the chip. |
Connect R5, the 47 kΩ pull-down, from BUS to 0 V and put the channel 3 tip on BUS. Power the UNO through its normal Universal Serial Bus (USB) connector. The UNO's 5V pin supplies this fixture. Use that one supply for the controller and buffer. Leave any external supply disconnected from the board. Set the scope inputs to direct-current coupling and high impedance, usually 1 MΩ at the instrument with the probe attached. Select the real 10× setting on every channel. All probe ground clips go to 0 V. Leave BUS disconnected from any receiving logic, other voltage source or 50 Ω instrument input.
R3 and R4 pull the enable pins high while the controller pins are inputs, including during reset once the shared rail is valid. These resistors draw about 0.5 mA each when the controller drives low. R5 sets a resting voltage for the released node and helps discharge its capacitance during the gap. A 10 MΩ probe in parallel with R5 changes the 47 kΩ nominal resistance by less than 0.5%. Output leakage and real probe capacitance still affect a released wire.
A break-before-make handoff releases the first driver and leaves a gap, called dead time, before enabling the second. If opposing outputs drive at once, each tries to force its own voltage on the shared node. That overlap is called contention.
For a first calculation, use 5.00 V for the active high output and 0 V for the active low output. When only A drives, R1 and R5 form a voltage divider. The ideal BUS voltage is 5.00 × 47 / (47 + 2.2), or about 4.78 V. When both drive, the low side is R2 in parallel with R5, about 2.10 kΩ. The node then sits near 5.00 × 2.10 / (2.20 + 2.10), or 2.44 V. About 1.16 mA leaves A, 1.11 mA enters B and 0.052 mA returns through R5. The current from A equals the sum of the currents into B and through R5. Real output voltages, resistor tolerance and probe loading can move the plateau.
For a conservative resistor-only bound, use the fixture's maximum 5.25 V rail and a 2.2 kΩ resistor at its 1% low limit, or 2178 Ω. Each output branch stays at or below 5.25 / 2178, or 2.41 mA, for node and pin voltages inside the shared rails. That bound covers a node accidentally held at either rail while both resistors remain in their respective paths. An opposing-output path through R1 and R2 alone would carry at most 1.21 mA. A shorted branch resistor defeats the fixture. Before power-up, measure each resistor independently and confirm there is no jumper around it. Leave both resistors fitted for every command.
TI specifies a 2–6 V recommended supply range. The ±35 mA per-output and ±70 mA supply or ground entries describe absolute stress ratings. The SN74HC125 electrical table gives output voltage limits at 4.5 V with a 6 mA test load. Our smaller resistor-limited loads serve this fixture. Use a measured 4.75–5.25 V supply at U1. At the datasheet's 4.5 V test supply, the minimum high input is 3.15 V and maximum low input is 1.35 V. These values are test-condition limits. The bench check below uses its own conservative observed control limits. A receiving circuit could interpret a midrail node unpredictably. Keep this node on instruments only.
g once. OE_A should rise before OE_B falls. Measure from the midpoint of OE_A's rise to the midpoint of OE_B's fall. Inspect BUS between the edges. The falling node shows stored charge leaving through R5 and the attached circuit. The decay depends on the fixture.o once, with both series resistors still fitted. OE_B should fall before OE_A rises. Measure that interval and inspect the midrail plateau. If you have a fourth channel, use it on the chip side of R1 or R2 in a repeat capture to estimate branch current from the voltage difference to BUS. Use the same ground and corresponding time window. Do not attach a grounded clip across a resistor. If a plateau is missing, first compare the order of the control edges and then verify the branch pins with power disconnected.If the gap is very short or the shared node has more capacitance, BUS can still be above ground when B turns on even though A released first. A low BUS voltage on its own also cannot tell you which device drove it. Read the control traces alongside BUS. The separately documented four-wire fan fixture uses the different SN74AHCT125N variant for a single command wire. Its input threshold and load assumptions belong to that circuit.
Each recognized command starts with A active for 10 ms and finishes with B active for 10 ms. It then releases both channels again. Characters other than lowercase g and o are ignored. Send commands individually so the scope can rearm. The sketch uses the order of ordinary pin writes for clarity. The archive's host test compiles this exact file with simulated input, output and delay calls. Its times describe the simulated calls. The bench worksheet has no observations, and no UNO build or physical measurement is included.
#include <Arduino.h>
constexpr uint8_t kEnableA = 7;
constexpr uint8_t kEnableB = 8;
constexpr unsigned int kComparisonUs = 10;
constexpr unsigned long kPlateauMs = 10;
void handoff(bool overlap) {
digitalWrite(kEnableA, LOW);
delay(kPlateauMs);
if (overlap) {
// The two series resistors must be fitted for this case.
digitalWrite(kEnableB, LOW);
delayMicroseconds(kComparisonUs);
digitalWrite(kEnableA, HIGH);
} else {
digitalWrite(kEnableA, HIGH);
delayMicroseconds(kComparisonUs);
digitalWrite(kEnableB, LOW);
}
delay(kPlateauMs);
digitalWrite(kEnableB, HIGH);
}
void setup() {
digitalWrite(kEnableA, HIGH);
digitalWrite(kEnableB, HIGH);
pinMode(kEnableA, OUTPUT);
pinMode(kEnableB, OUTPUT);
Serial.begin(115200);
Serial.println("Ready: g=guarded gap, o=resistor-limited overlap.");
}
void loop() {
if (Serial.available() == 0) {
return;
}
const int command = Serial.read();
if (command == 'g' || command == 'o') {
handoff(command == 'o');
Serial.println("Handoff complete. Both outputs disabled.");
}
}
Suppose you remove R5 with power disconnected and then repeat only the guarded handoff. What changes during the gap, and why would the logic-control trace still show the same order?
While both buffers are disabled, the node has lost its defined discharge path. It can briefly retain charge, and probe resistance or leakage can eventually move it. The two control lines still follow the commanded order, but BUS may stay high longer and then fall when B becomes active. Keep both series resistors in place. Their role is separate from the pull-down's role.