Build a 3.00 V fixture around one Texas Instruments SN74LVC1G57DBVR. Measure all eight input combinations, then use two fixed wiring configurations to obtain a two-input AND gate and a two-input NOR gate. Each result is a voltage you can check at the package. The worksheet records the actual input voltages, so a miswired input cannot hide behind a correct-looking output.
A truth table lists the output for every combination of inputs. A strap is a physical wire that fixes one input to a supply rail. All three pins on this part are ordinary logic inputs. The level on a strapped pin continues to affect the output throughout the run. There is no configuration register to write. The Python program reads the worksheet after the experiment.
| DBV pin | Signal | Connection for the eight-row run |
|---|---|---|
| 1 | In1 | Junction of S1 to VCC and R1 to GND. |
| 2 | GND | Supply return, capacitor return, pull-down returns and meter COM. |
| 3 | In0 | Junction of S0 to VCC and R0 to GND. |
| 4 | Y | Logic output to R3, then the TP_Y meter test point. |
| 5 | VCC | 3.00 V supply, C1 and the switched high rail. |
| 6 | In2 | Junction of S2 to VCC and R2 to GND. |
At each input, the 10 kΩ resistor is a pull-down. It provides a path to ground when the switch is open, so the chip sees logic 0. Closing the switch connects that input to VCC, the positive supply, for logic 1. Fit all three modules before enabling the supply. The DBV has no unconnected pin. In the strap runs, the input that no longer needs a switch still needs a deliberate rail connection. TI’s recommended supply range is 1.65 V to 5.5 V. The 6.5 V absolute maximum supply rating is a stress limit.
At the top of the fixture’s rail window, 3.05 V across a 10 kΩ nominal pull-down draws about 0.305 mA and dissipates about 0.93 mW. Three closed switches draw about 0.915 mA through their pull-downs. With the meter attached at TP_Y, R3 and the nominal 10 MΩ meter input form a divider. At 3.05 V their series current is about 0.305 µA, and the drop across R3 is about 0.305 mV. A direct short at TP_Y would draw about 3.05 mA from an ideal high output through nominal R3. This estimate explains the series resistor. It does not qualify the chip for accidental shorts or external drive. Leave LEDs, other logic outputs and external supplies off TP_Y.
The inputs have Schmitt triggers, which use different thresholds for rising and falling voltages. At the 3.0 V test point, TI specifies the rising threshold from 1.50 to 1.87 V and the falling threshold from 0.84 to 1.19 V. Use rail-level input changes and let the voltage settle. The program’s input guard bands are 0 to 0.25 V for low and VCC minus 0.25 V to VCC for high. Its output guard bands are 0 to 0.20 V for low and VCC minus 0.20 V to VCC for high. Here VCC is the measured supply on that worksheet row. These are fixture checks, with the rail restricted to 2.95–3.05 V. They do not measure thresholds or replace TI’s voltage and load conditions. TI specifies a low output up to 0.1 V and a high output at least VCC minus 0.1 V at the corresponding 100 µA load conditions.
000. Set the supply to 3.00 V and the current limit to 10 mA. Enable the output. Stop and inspect the wiring if the supply enters current limit or the rail at pin 5 lies outside 2.95–3.05 V. Use pin 2 as the meter reference.full row of the worksheet.| In2 · pin 6 | In1 · pin 1 | In0 · pin 3 | Y · pin 4 |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
The first four rows show that when In2 is 0, Y is the inverse of In0. The last four show that when In2 is 1, Y equals In1. This split predicts the two straps. For example, with In0 fixed high, the branch for In2 low always yields 0, and the branch for In2 high follows In1. That is the behavior of an AND gate on In2 and In1.
For the AND configuration in TI Figure 4, disable the supply and check that VCC has discharged. Remove the S0/R0 module from In0 and tie pin 3 to VCC. Leave S1/R1 and S2/R2 connected. Run the four and worksheet rows, measuring pin 3 every time along with the other inputs. AND produces a high output only when both live inputs are high.
For the NOR configuration in TI Figure 7, disable the supply and check that VCC has discharged again. Remove the VCC strap from pin 3 and reconnect its S0/R0 module. Remove the S1/R1 module from In1 and tie pin 1 to GND. Leave S2/R2 connected. Run the four nor worksheet rows and measure pin 1 every time. NOR means inverted OR, so its output is high only when both live inputs are low. In each configuration the disconnected module has no path to the strapped pin. Reconnect neither module nor strap while the supply is enabled.
| A | B | AND Y | NOR Y |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 |
B is In2 in both configurations. A is In1 for AND and In0 for NOR. Use the physical In2, In1, In0 order in the worksheet, even when the two-variable table above uses A and B.
Make a copy of the blank comma-separated values (CSV) worksheet and fill its five voltage columns in volts. Keep the header and the mode and bit columns intact. The and rows fix the last bit to 1, and the nor rows fix the middle bit to 0. Save the copy as observations.csv in the same directory as truth_table.py, then run python3 truth_table.py observations.csv. The code below is complete.
#!/usr/bin/env python3
"""Check settled SN74LVC1G57 worksheet readings against TI SCES414P Table 1."""
import argparse
import csv
import itertools
import sys
from decimal import Decimal, InvalidOperation
COLUMNS = ("mode", "in2", "in1", "in0", "vcc_v", "in2_v", "in1_v", "in0_v", "y_v")
Y_TABLE = (1, 0, 1, 0, 0, 0, 1, 1)
SUPPLY_MIN = Decimal("2.95")
SUPPLY_MAX = Decimal("3.05")
INPUT_BAND = Decimal("0.25")
OUTPUT_BAND = Decimal("0.20")
def expected_rows():
"""Keep row order and fixed strap levels explicit."""
rows = [("full", *bits) for bits in itertools.product((0, 1), repeat=3)]
rows.extend(("and", in2, in1, 1) for in2, in1 in itertools.product((0, 1), repeat=2))
rows.extend(("nor", in2, 0, in0) for in2, in0 in itertools.product((0, 1), repeat=2))
return rows
def expected_y(in2, in1, in0):
return Y_TABLE[4 * in2 + 2 * in1 + in0]
def level(volts, supply, band):
"""Classify a settled rail reading within the experiment's guard bands."""
if volts < 0 or volts > supply:
return None
if volts <= band:
return 0
if volts >= supply - band:
return 1
return None
def parse_voltage(raw, line, name):
try:
value = Decimal(raw.strip())
except (InvalidOperation, ValueError) as error:
raise ValueError(f"line {line}: {name} requires a numeric reading") from error
if not value.is_finite():
raise ValueError(f"line {line}: {name} must be finite")
return value
def read_rows(source):
reader = csv.reader(source)
if tuple(next(reader, [])) != COLUMNS:
raise ValueError(f"header must be {','.join(COLUMNS)}")
allowed = set(expected_rows())
readings = {}
for line, cells in enumerate(reader, start=2):
if len(cells) != len(COLUMNS):
raise ValueError(f"line {line}: expected {len(COLUMNS)} columns")
if any(bit not in ("0", "1") for bit in cells[1:4]):
raise ValueError(f"line {line}: planned inputs must be 0 or 1")
bits = tuple(int(bit) for bit in cells[1:4])
key = (cells[0], *bits)
if key not in allowed:
raise ValueError(f"line {line}: unexpected mode or strap row {key}")
if key in readings:
raise ValueError(f"line {line}: duplicate row {key}")
readings[key] = tuple(
parse_voltage(raw, line, name) for raw, name in zip(cells[4:], COLUMNS[4:])
)
missing = [key for key in expected_rows() if key not in readings]
if missing:
raise ValueError(f"missing {len(missing)} worksheet rows, first missing {missing[0]}")
return readings
def assess_row(key, readings):
mode, *planned = key
supply, *nodes = readings
want = expected_y(*planned)
if not SUPPLY_MIN <= supply <= SUPPLY_MAX:
return want, None, [f"VCC {supply} V is outside the fixture range"]
faults = []
for name, volts, bit in zip(("In2", "In1", "In0"), nodes[:3], planned):
observed = level(volts, supply, INPUT_BAND)
if observed != bit:
observed_text = "outside the input bands" if observed is None else str(observed)
faults.append(f"{name}={volts} V reads {observed_text}, expected {bit}")
seen = level(nodes[3], supply, OUTPUT_BAND)
if seen != want:
observed_text = "outside the output bands" if seen is None else str(seen)
faults.append(f"Y={nodes[3]} V reads {observed_text}, expected {want}")
return want, seen, faults
def check(source, output):
readings = read_rows(source)
passed = 0
for key in expected_rows():
mode, *bits = key
want, seen, faults = assess_row(key, readings[key])
bit_text = "".join(map(str, bits))
observed = "?" if seen is None else str(seen)
status = "PASS" if not faults else "CHECK"
print(f"{mode:4} {bit_text} expected={want} observed={observed} {status}", file=output)
for fault in faults:
print(f" {fault}", file=output)
passed += not faults
total = len(readings)
print(f"{passed}/{total} rows pass the settled-voltage checks.", file=output)
return 0 if passed == total else 1
def main():
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument("csv_file", help="filled copy of observations-blank.csv")
arguments = parser.parse_args()
try:
with open(arguments.csv_file, encoding="utf-8-sig", newline="") as source:
return check(source, sys.stdout)
except (OSError, ValueError, csv.Error) as error:
print(f"Worksheet error: {error}", file=sys.stderr)
return 2
if __name__ == "__main__":
raise SystemExit(main())
The program reports the expected and observed output for every row. It returns 0 if all rows pass, 1 if any rail, input or output reading fails a fixture check, or 2 if the worksheet cannot be read as the prescribed set of 16 rows. Fix the first unexplained input error before interpreting a wrong output. A voltage between the bands or outside the supply rails calls for a wiring or meter check. If Y appears constant, verify the actual levels at pins 6, 1 and 3 and check continuity across R3. If a strap is correct and the output is wrong, revisit chip orientation, supply bypassing and the pin 4 probe location.
This experiment checks settled logic. A meter can miss contact bounce and fast output pulses, and it cannot determine propagation delay from these readings. For a different use of truth tables, see the SN74HC86 even-parity experiment, which exercises several fixed exclusive-OR gates together.
With all three modules fitted, the switch labels say 001 and 010. The measured outputs are 1 and 0 respectively. Which two input labels would you check first?
Check whether In1 and In0 have been swapped between pins 1 and 3. At In2 low, Y follows the inverse of the actual In0 voltage. Measure pins 1 and 3 in both rows. Output alone cannot establish the wiring fault.