Tricky Circuit

A binary counter and clock divider

Count events with four lights

A clock is a repeating timing signal; CLK abbreviates Clock. A rising edge is its change from logic 0 to 1. A binary counter adds one per received rising edge. A bit is a binary digit, 0 or 1; four bits hold 16 states, 0000 to 1111. Hz (hertz) counts cycles per second.

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EXPERIMENT BENCH

Change the circuit settings, predict the readings, then check a challenge. These are learning models, with the assumptions explained in each lesson.

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How it works

Choose 0–32 already-received edges or press Clock pulse to add one. This is a history sample, not an automatically running clock. Frequency sets steady repeating output rates, not the chosen count. Ideal transitions have no delay or contact bounce. Clock pulse stops at 32 received edges. Reset starts a new sample.

n is the number of received edges. The four-bit count is n modulo 16: keep the remainder after division by 16. Q0 is the lowest-weight bit and Q3 the highest. Under continuous counting, Q0 completes one cycle per two edges; Q3 per sixteen.

Difficulty

  1. Build · Observe

    Power on. Choose 3 received edges and 8 Hz. Obtain count 3, binary 0011.

    Need a hint?

    n=3; f=8 Hz → 0011

  2. Explore · Experiment

    At 8 Hz choose 16 received edges. Observe wraparound to count 0, binary 0000.

    Need a hint?

    n=16; f=8 Hz → 0000

  3. Solve it · Solve

    Choose 19 edges and 16 Hz. Obtain count 3, Q0 frequency 8 Hz and Q3 frequency 1 Hz.

    Need a hint?

    n=19; f=16 Hz → 0011; fQ0=8 Hz; fQ3=1 Hz

Extra reading and circuit recipes

A binary counter and clock divider

Each indicator has a place value, like decimal digits in an odometer. The rightmost bit changes fastest. Watching the same counter as a timing circuit reveals progressively slower rhythms.

count = n mod 16; fQ0 = fCLK/2; fQ3 = fCLK/16

Count and frequency answer different questions: how many edges have arrived, and how often a repeating waveform cycles. Changing clock frequency does not rewrite the selected history.

A useful connection

A bit toggles each time it changes state; two toggles make a full cycle. This is why Q0 is f/2, not f.

A surprising detail

Wraparound does not mean events vanished. Four bits keep only the remainder; a wider counter can retain more.

A useful trap to avoid

A clock held high is not many rising edges. A real push-button can bounce and produce extra edges; one simulated press is one clean edge.

A four-bit counter at 15 receives one more rising edge. Its count becomes…

  1. 0
  2. 16
  3. 15
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Only 16 states fit. The sequence wraps from 1111 to 0000.

Small event counter

Select three clean received edges.

The displayed four-bit word is 0011.

Divide the rhythm

Select a 16 Hz clock and nineteen received edges.

Count is 3; steady Q0 cycles at 8 Hz and Q3 at 1 Hz.

Try another change

Move from 15 to 16 to 17 received edges. Predict 1111, 0000 and 0001 first. Then change only frequency and check that the displayed count stays unchanged.

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