Tricky Circuit

A one-bit SR latch

Teach a circuit to remember

SR means Set Reset: set writes 1, reset writes 0. A latch stores one bit, a binary digit that is 0 or 1. Two NOR (NOT OR) gates feed their outputs back to each other. A NOR output is 1 only when both inputs are 0. Here logic 1 is 5 V and logic 0 is 0 V.

Open interactive experiment

EXPERIMENT BENCH

Change the circuit settings, predict the readings, then check a challenge. These are learning models, with the assumptions explained in each lesson.

Sign in to save progress. Guest progress stays on this device.

Open laboratory in a full window

How it works

Ideal active-high inputs: 1 activates the command. S = R = 1 is invalid. Releasing both then leaves memory uncertain until one command acts. Power off resets this teaching model to 0; a real latch has no guaranteed power-up state. Delays and noise are omitted. Use Release both inputs to return S and R to 0 together.

S is set, R is reset, Q is stored output, and Q̅ is its opposite in valid operation. With S = R = 0, feedback keeps the previous bit. Both commands at 1 force both outputs to 0, so they cease to be opposites.

Difficulty

  1. Build · Observe

    Power on. Set S = 1 and R = 0 to obtain Q = 5 V.

    Need a hint?

    S=1; R=0 → Q=5 V

  2. Explore · Experiment

    First set S = 1, R = 0, then release S to 0. Keep R = 0 and prove Q still equals 5 V.

    Need a hint?

    S=1; R=0 → S=0; R=0 → Q=5 V

  3. Solve it · Solve

    Set S = 0 and R = 1. Obtain Q = 0 V and Q̅ = 5 V.

    Need a hint?

    S=0; R=1 → Q=0 V; Q̅=5 V

Extra reading and circuit recipes

A one-bit SR latch

Imagine a door sensor that flashes for an instant. Without memory, the event disappears before you look. Cross-coupled gates turn that brief event into a visible state you can acknowledge later.

S,R = 00 → Qprev; 10 → Q=1; 01 → Q=0; 11 → Q=Q̅=0

The truth table needs a previous state: inputs 00 mean hold, not write zero. The barred symbol Q̅ means the complementary output; it is not a negative voltage.

A useful connection

A brief alarm event can be remembered after the sensor returns to normal. A separate reset acknowledges it.

A surprising detail

Feedback stores the state only while the real circuit has suitable power. This latch is not permanent storage.

A useful trap to avoid

Never use S = R = 1 as a normal memory command. Releasing it does not reliably choose a stored bit.

After a valid set, both inputs return to 0. Q…

  1. stays 1
  2. becomes 0
  3. oscillates automatically
Read more

The two gates reinforce the existing state. No reset command occurred.

Remember an alarm

Apply set; then move S back to 0 without touching R.

Q is 5 V during set and remains 5 V after release.

Acknowledge the alarm

Apply reset with set released.

Q becomes 0 V; releasing reset then preserves 0.

Try another change

Try S = R = 1, release both, and observe uncertainty. Recover by asserting only reset. Compare this with an ordinary valid hold.

bob.cs.sonoma.edu